This invention relates to a hybrid semiconductor integrated circuit device. More particularly, the present invention relates to technique which will be effective when applied to a hybrid semiconductor integrated circuit device (hereinafter referred to as "Bi-CMOS") fabricated by integrating bipolar transistors and complementary MISFETs (CMOSs) on the same semiconductor substrate.
Development of hybrid semiconductor integrated circuit devices by integrating bipolar transistors and complementary MISFETs on the same semiconductor substrate has been carried out. In the hybrid semiconductor integrated circuit devices, a dielectric breakdown prevention circuit is inserted between external terminals (bonding pads) and an input stage circuit.
Generally, this dielectric breakdown prevention circuit comprises a resistance element and a clamp MISFET. The resistance element comprises an n-type semiconductor region (a diffusion layer resistor) formed on the main plane portion of a p-type semiconductor substrate (a well region, in practice). One of the ends of this resistance element is connected directly to the external terminal and its other end, to the input stage circuit through a drain region of clamp MISFET. The resistance element reduces an excessive current (transient current) that is inputted to the external terminal and will otherwise cause dielectric breakdown, or absorbs it to the side of the semiconductor substrate by breakdown (reversible breakdown). The breakdown of the latter is generated by the n-type semiconductor region as the resistance element and a diode device defined by a p-n junction portion with the p-type semiconductor substrate. The clamp MISFET has an n-channel and its drain region is formed integrally with the other end of the resistance element.
The source region and gate electrode of the clamp MISFET are connected to a reference potential, e.g. 0 [V], respectively. The clamp MISFET is constituted so as to absorb the excessive current passing through the resistance element by surface breakdown or zenor breakdown, to the semiconductor substrate side. Each of the breakdown voltages (junction with stand voltages) of the clamp MISFET are set to be lower than the dielectric breakdown voltage of the gate insulation film of the complementary MISFET of the input stage circuit.
In the dielectric breakdown prevention circuit having the construction as described above, the excessive current inputted to the external terminal is reduced by the resistance element and is clamped by the clamp MISFET. In this manner this circuit can prevent the breakdown (dielectric breakdown) of the gate insulation film of the input stage circuit. Since the resistance element and the clamp MISFET of the dielectric breakdown prevention circuit can be fabricated by the same production step as MISFETs of an internal circuit or the like, the dielectric breakdown prevention circuit is characterized in that the number of production steps of the hybrid semiconductor integrated circuit device can be reduced.
The hybrid semiconductor integrated device which is now being developed by the present inventor and is not therefore a prior art accomplishes a high integration density in accordance with the rule of proportional contraction. It employs a 0.8 [.mu.m] fabrication process. This 0.8 [.mu.m] process is the one that can form the minimum fabrication dimension such as the gate length of the gate electrode of MISFET and the width of wirings at 0.8 [.mu.m]. If such a fabrication process is employed, the gate insulation film of MISFET of an internal circuit or an input stage circuit can be formed by an about 20 [nm]-thick thin film in accordance with the rule of proportional contraction described above. The dielectric breakdown voltage of this gate insulation film having such a small thickness is about 19 [V]. On the other hand, the impurity concentrations of the n-type semiconductor region and p-type semiconductor substrate forming the resistance element and the clamp MISFET of the dielectric breakdown prevention circuit are not increased against the rule of proportional contraction for the purpose of reducing the increase in a parasitic capacitance or because the number of fabrication steps increases. This means that the p-n junction withstand voltage (breakdown voltage) between the drain region (high impurity concentration) of the resistance element and clamp MISFET and the semiconductor substrate (low impurity concentration) does not substantially change with a higher integration density. This p-n junction withstand voltage is about 20 [V]. In other words, the dielectric withstand voltage of the gate insulation film of the complementary MISFET of the input stage circuit is lower than the junction withstand voltage of the resistance element and clamp MISFET of the dielectric breakdown prevention circuit. Therefore, when an excessive current is inputted to the external terminal, there occurs frequently the phenomenon that the input stage circuit undergoes dielectric breakdown before the dielectric breakdown prevention circuit absorbs this excessive current.
Accordingly, the inventor of the present invention improves the dielectric breakdown voltage of the hybrid semiconductor integrated circuit device by employing the technique disclosed in Japanese Patent Application No. 136100/1988 that was filed previously. This technique forms each of the resistance element and clamp MISFET of the dielectric breakdown prevention circuit by an n-type semiconductor region having a high impurity concentration and brings the bottom surface of this n-type semiconductor region into contact with a buried type p-type semiconductor region having a high impurity concentration. The n-type semiconductor region having a high impurity concentration is formed by the same fabrication step as a collector potential pull-up semiconductor region which pulls up a collector potential from the buried type collector region of an n-p-n bipolar transistor of a vertical structure to the surface of the semiconductor substrate. The buried type p-type semiconductor region having a high impurity concentration is formed by the same fabrication step as the buried type p-type semiconductor region of a device isolation region which defines the periphery of the bipolar transistor described above. In other words, this dielectric breakdown prevention circuit constitutes the diode device by the n-type semiconductor region having a high impurity concentration and the p-type semiconductor region having a high impurity concentration, and reduces the p-n junction withstand voltage (breakdown voltage). This p-n junction withstand voltage is from about 10 to about 16 [V]. Accordingly, since the dielectric breakdown prevention circuit mounted to the hybrid semiconductor integrated device which is under development by the present inventor can absorb the excessive current before the occurrence of dielectric breakdown of the input stage circuit, it can improve the dielectric breakdown withstand voltage. Incidentally, Bi-CMOS devices are described in U.S. patent application Ser. No. 07/029,681 by Yutaka KOBAYASHI et al, filed Mar. 24, 1987.